资源列表
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
vend
- 自动售货机，根据所要的东西，自动收费，并进行找零-Vending machine, according to what you want to automatically charge and conduct Keep the change
s3edisp_schem
- This document is a entire schematic of SPARTAN3 DSP Development Board.
10_code_ALTERA7128SLC84
- 10个FPGA实验的源代码，用VHDL编写，是一个试验箱的开发手册-10 CPLD experiment, the source code
sopc_altera_monitor_program
- This book descripe sample example to use altera monitor wih quartes
tut_sopc_introduction_vhdl_2
- This book descripe how use altera monitor program with sopc fpga by verilog language
sopc_builder_tutorial
- This application ready to run about use altera monitor program with de2 sample processor
ASY_FIFO
- 用Verilog编写的异步FIFO，可以方便的实现同步异步的转换，在全局异步局部异步的系统中得到广泛应用-ASY_FIFO written with verilog,and it is very useful in a GALS system
DDS_VHDL
- 基于FPGA环境的直接数字频率合成器的源代码-16 accumulator
VHDLdesign
- vhdl基础详解，有实例分析，适合初级eda学者学习-vhdl-based Xiang Jie, there is a case study, for academics to study the primary eda
clockVHDL
- 采用自顶向下设计方法，由秒计数模块、分计数模块、时计数模块、时间设置模块和译码模块五部分组成。-Using top-down design methodology, from the second counter module, sub-counting module, when the counting module, time setting module and decoding module of five parts.
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件，简单，实用-VHDL-based Digital Clock Design Courseware