资源列表
System_Verilog_training
- montor的system verilog培训教程-system verilog training material from mentor
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vprimer
- 硬件語言VERILOG介紹及範例. 適合初學者.-Verilog language Introduction and Examples.
Verilog-r2
- VLSI之硬體語言設計 --使用verilog 中文版.-VLSI hardware language design- Use Verilog.
HDL_design_stile
- HDL编码风格与编码指南. 包括: 1.命名规则 2.编码指导-HDL coding style and coding guidelines. Include: 1. Naming rules 2. Coding guide
CMU_verilog
- 歐美某大學之verilog 語言介紹,包括設計方法與結構.-CMU introduced the verilog language, including design methods and structures.
IIC
- fpga实现的IIC通信的例程，注释很详细-fpga implementation of serial communication routines, comments in great detail
16bit_mult
- 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
FPGA-LCD
- VHDL文章：以FPGA为核心的液晶显示电路设计与实现-VHDL article: The FPGA as the core liquid crystal display circuit design and implementation of
FPGA-LCDdriver
- EDA技术相关文章：基于FPGA的LCD驱动芯片设计-EDA technology-related articles: FPGA-based LCD driver IC design
pojie
- quartus II中文用户教程Quartus II 中文用户指-wu
clock_counter
- 一个简易的时分秒自加计数器，没有设置功能-hour-minute-second counter