资源列表
DE2_CAMERA
- 基于DE2实验开发平台的CMOS相机图像采集程序。-DE2 board CMOS camera image acquisition program.
VGA_Display
- 基于VGA接口的Verilog语言程序，包括VGA接口时序控制以及图案生成模块。-VGA interface based on Verilog language program, including VGA interface timing control, and pattern generation module.
shuzizhong
- 实现数字钟设置与查看 秒表 以及闹钟设置与查看-Digital clock stopwatch and alarm clock
VGA-RefComp
- 在开发板Basys2中实现VGA接口设计，该设计在Basys2开发平台中测试过，没有问题-Implemented in the development board Basys2 VGA interface design, which in Basys2 development platform tested, there is no problem
ml605_FMC_Si570_Prog_rdf0047_13.4_c
- 该源码是基于xilinx ml605开发板扩展接口FMC的设计，在开发板中插入子卡，程序在开发板中测试通过。-The source is based on xilinx ml605 development board FMC expansion interface design, the development board daughter card is inserted, the program development board test.
ml605_MIG_rdf0011_13.4_c
- 该参考程序是基于xilinx ml605开发板的一个DDR3参考设计，源文件包含相应的管脚约束文件。-The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
ml605_PCIe_Gen1_x8_rdf0008_13.4_c
- 该压缩文件为一个pcie接口设计源程序，源程序包含一个8通道gen1的pcie IP CORE和相应的用户接口程序，烧到开发板ml605中测试通过。 -The compressed file is a pcie interface design source code, source code contains an 8-channel gen1 of pcie IP CORE and the corresponding user interface program, burn developm
ml605_PCIe_Gen2_x4_rdf0009_13.4_c
- 该压缩文件为一个pcie设计源文件，pcie为一个4通道的pcie设计。文件中包含pcie IP CORE和相应的参考程序，在ml605开发板中测试通过。-The compressed file is a pcie design source files, pcie pcie is a four-channel design. Files contain pcie IP CORE and the corresponding reference program in ml605 developme
Freq
- 该源程序为一个频率发生器，可以产生不同频率的时钟信号，上开发板测试通过。-The source is a frequency generator that can generate clock signals of different frequencies, the development board test.
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
jianyiluojifenxiyi
- 基于verilog 的简易逻辑分析仪，已经过调试-Simple verilog based logic analyzer, has been testing