资源列表
WITH_SDRAM_DAQ
- pci控制器中的管脚分配部分，完成pin分配-pci controller pin assignment section, complete pin assignment
EDA
- EDA重点内容，附带HDML文件-EDA highlights, with HDML files! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
ASK--vhdl
- ASK调制与解调VHDL程序及仿真 ask的调制解调使用VHDL语言-ASK modulation and demodulation process and VHDL simulation ask modulation and demodulation using VHDL language
VHDL-
- 8位相等比较器，布斯乘法器，以为寄存器的VHDL实现-Eight for phase comparator, Booth multiplier, that registers of VHDL
tlc5615
- 基于FPGA 的tlc5615 的实现，经过了自己的验证，能正常使用-Tlc5615 FPGA-based realization, through its own validation, can be used normally
DS18B20
- DS1302Z 读取和设置RTC，时间显示在数码管 在FPGA上实现。课正常使用-[DS1302Z]: read and set the RTC, the time displayed on the digital implemented on FPGA. Lesson normal use
DS1302Z_RTC
- 10_RTC[DS1302Z] ：读取和设置RTC，时间显示在数码管 自己试验，课直接使用-10_RTC [DS1302Z]: read and set the RTC, the time displayed on the digital test their own, direct use of classes
TLC5615_1k
- 进阶实验_12_DA[TLC5615]_1：通过DA输出正弦波，频率1KHz-Advanced experimental _12_DA [TLC5615] _1: By DA output sine wave, frequency 1KHz
FPGASPI
- FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信-FPGA SPI Timing interpretation covering all main modules communicate with the DSP
Experiment-37-verilog-program
- 本文收集了37个利用verilog语言编写的实验程序-This collection of 37 using the experimental procedure verilog language
TLC5615_1-10k
- 进阶实验_13_DA[TLC5615]_2：通过DA输出方波，频率可调，1K~10KHz，步进1K-Advanced experimental _13_DA [TLC5615] _2: By DA output square wave, frequency adjustable, 1K ~ 10KHz, stepping 1K
PWM
- FPGA产生PWM波控制小车，Verilog语言编写，实现简单的正、反、停控制-FPGA generate PWM wave to control the car, Verilog language, to achieve a simple positive and negative, stop control