资源列表
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
cordic
- cordic一次移位，需要多次的话可以通过多次条用-codic algorithm unit
LPF_module
- 用verilog实现带宽可调的低通滤波器-Verilog to achieve the low-pass filter with adjustable bandwidth
basketballcounter
- a basketballscore counter two band 0--a basketballscore counter two band 0-999
FT245BL_test
- this a example for the mouse vga for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
mod10counter
- 用D触发器实现的模10计数器，Xilinx14.4ISE编译通过-Implemented using D flip-flop mode 10 counters, Xilinx14.4ISE compiled by
VHDL-code-specification
- vhdl的代码规范。包括命名、语句使用等。注重可移植性以及硬件资源的节约。-vhdl code specifications. Including naming, such statements use. Attention to portability and hardware resource conservation.
shj
- 基于fpga的自动售货机，verilog编写，源码内有详细说明-Fpga-based vending machine, verilog prepared with a detailed descr iption of source
seg7
- fpga上nios处理器avalon总线数码管驱动，包含任务逻辑，寄存器，和接口的verilog HDL描述-fpga nios processor avalon bus on digital tube driver, including the task logic, registers, and interfaces verilog HDL descr iption
zs
- 基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改-Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire
doorlock
- doorlock 用verilog语言描写门锁功能-door lock function using verilog language descr iption
nexis1
- 用Verilog HDL 状态机实现的驱动数码管显示，是个很不错的模块，可以直接用-Using Verilog HDL state machine driven digital display, is a very good module, can be directly used