资源列表
tlc549adc
- 本程序是用Verilog HDL 状态机编写的tlc549的驱动程序-This procedure is used to write Verilog HDL state machine driver tlc549
TLC5620v
- 本程序是用verilog 状态机编写的tlc5620的驱动程序，可以直接调用-The program is written in verilog tlc5620 state machine driver, you can directly call
11_lcd1602
- 本程序是用verilog 状态机编写的lcd1602的驱动程序，可以直接调用-The program is written in verilog lcd1602 state machine driver, you can directly call
volt_mea_disp
- 本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值-This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value
lcd_12864_dirive
- HS12864的驱动，verilog语言编写，，，，，希望有用-HS12864 drive, verilog language,,,,, I hope useful
display
- 实现了Verilog语言驱动数码管，扫描稳定。无抖动。可是很清晰的显示字符-Implements the Verilog language-driven digital control
spi_verilog
- 使用verilog编写的spi传输模块，已经通过验证，有仿真文件，可以传输信息。-Prepared using verilog spi transmission module, has been validated with simulation files, you can transfer information.
DDS
- DDS信号源实现源码，实现正弦波、方波、三角波等，频率、相位可调。-DDS signal source to achieve source
1602Pkeyscan
- 基于FPGA的lcd1602以及矩阵按键扫描程序（verilog）-FPGA-based lcd1602 and matrix key scanning program (verilog)
filter
- 滤波器，经过modelsim仿真得到了正确的结果-Filter through modelsim simulation get the correct result
shumaguan
- 各种数码管显示源码，七段，八段，共阳共阴都有，且都经过仿真得到正确的波形 -Various digital display source, segment, eight out of a total of yin yang are, and have been to get the correct waveform simulation
dingshi
- 定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确-Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct