资源列表
count
- 各种常用计数器模块，加减可控计数器和模可变计数器等等，经过仿真得到了正确的波形-Various common counter module, subtraction controllable variable modulus counter counter and so on, through simulation to get the correct waveform
duoji
- 基于FPGA的，运用Verilog语言编写的，通过黑线检测来控制舵机的程序。-FPGA-based, using Verilog language, through the detection of black lines to control the steering process.
8051based_on_Verilog
- 8051的内核的verilog实现,有完整源代码，部分注释-8051 core verilog achieve
Structural-UpDown-Counter
- Structural UpDown Counter
RAMFIFO_Ctrl_LFSR
- RAMFIFO with LFSR Controller
DistRAM
- Distributed Single Port RAM
FCS_16
- Frame Check Sequence 16 bit Generator (CRC-CCITT and CRC-16)
FIFO-Controller-with-LFSR
- FIFO Controller With LFSR
Structural-Pipeline-Multiplier
- Structural Pipeline Multiplier
tst8
- verilog编写的键盘接口程序，带串口测试-verilog prepared by the keyboard interface program with serial test
FPGA_NIOS_liushuideng
- 基于FPGA的NIOS处理器实现简单的流水灯功能-NIOS processor FPGA-based realization of a simple light water feature
fsm101101
- 基于quartusII软件的101101有限状态机设计实例，运用VHDL语言描述-101101 quartusII software based finite state machine design examples, the use of VHDL descr iption