资源列表
elevator_v2
- 用verilog语言描述的模拟单电梯的运行过程。方向优先原则。(1)每层电梯入口处设有上下请求按钮（一楼只有上请求，6楼只有下请求），电梯内设有顾客到达层次的停站请求开关。 (2)电梯入口处设有电梯当前所处楼层指示装置及电梯运行模式(上升或下降)指示装置。 (3)电梯每2秒升(降)一层楼。 (4)电梯到达有停站请求的楼层，经过1秒电梯门打开，开门指示灯亮，开门3秒后，电梯进入关门中状态，提示乘客可以按下延迟关门按键，此时指示灯闪烁，2秒后电梯门关闭，电梯继续进行，直至执行完最后一个
num_clock
- 基于DE0实验板开发的verilog数字钟程序。实现了12/24小时制切换；闹钟；整点报时等功能。-Based on experimental board development DE0 verilog digital clock procedures. To achieve a 12/24 hour switch alarm clock whole point timekeeping function.
eatfish
- vhdl语言，可以实现大鱼吃小鱼功能的时钟仿真仿真，经过测试可用-vhdl language, can achieve ones devour function clock simulation simulation, tested available
i2c_latest.tar
- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device (microcontroller, IP block).
vhdl_01110010
- 一个简易的产生巴克码和巴克码的检测程序，适合于刚刚学习VHDL语言的入门。-A simple code and generate Barker Barker code testing procedures, suitable for just learning VHDL language entry.
pulse_syn
- 跨异步时钟域单bit处理模式，工程实际应用中，非常有效。-Cross-domain single-bit processing asynchronous clock mode, practical application of engineering, is very effective.
8B10B
- 8b/10b编解码实现，很实用。可以借鉴-8b/10b encoding and decoding to achieve, very practical. Can learn
VHDL
- VHDL小程序，其中包含了bcd码转换成格雷码、寄存器的简单设计（并入串出移位寄存器、串入串出移位寄存器）以及脉冲发生器的VHDL实现。适合于基础的VHDL入门。-VHDL small program, which includes a bcd code into Gray code, register for a simple design (String into a shift register, the string into the string out of the shift re
ADDER
- 超前进位加法器。时序好，功能可靠.工程引用已经验证。-Lookahead adder. Timing is good, functional and reliable
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
vhdl
- NUTAQ 公司的RF 420M 的FMC接口代码 -NUTAQ company' s RF 420M of FMC interface code
Pattern_Generator
- vip套件中的彩条显示实例vga显示-vip suite color bar display example