资源列表
61EDA_C2345
- FPGA 开发与设计，适合新手开始对FPGA进行设计。希望有帮助-FPGA development and design, suitable for novice to begin FPGA design. Hope that helps
spimaster
- 一般AD的spi配置代码，考虑的采样的时序问题。-General AD, spi configuration code, consider a sampling of the timing problems.
61EDA_C2293
- 《设计与验证Verilog程序》书中的全部代码，很全-" Verilog Design and Verification procedures" all the code book, it is full
first-follow
- first follow集合生成器 我晕。还嫌我说的少-first bu jiushi shang chuan dong xi ma
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
examples
- Verilog源程序130例，对初入门者非常有用。-Verilog source code 130 cases, were very useful for beginner.
movedata
- 按照一定格式把一段数据放在内存上，然后输出在屏幕上-my asm
controller
- PI controller and its source code
updown_6
- 这是一个使用VHDL语言编写的六进制计数器，具有自动控制加计数或减计数的功能。-This is a VHDL language using the six binary counter, with automatic control plus or minus count count function.
counter_12
- 使用VHDL语言编写的十二进制计数器，有异步清零、同步置数的功能、-Using the VHDL language of the 10 binary counter, there are asynchronous clears, synchronous set the number of functions,
calc_v2_s3eboard
- Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
keyboard
- verilog实现键盘驱动功能，具备基本字母按键输入，大小写转换功能，通过串口与主机实现交互-verilog to achieve keyboard-driven features, basic letter keys input, case conversion functions, interact with the host computer through the serial port