资源列表
8051f
- 还是必要的用于社么都可以水电费撒发发啊阿发结案时间发了卡回复-Document Library
Dian.zhen
- FPGA开发，在8x8点阵上实现左右，上线滚动显示文字。以及变色显示文字。通过按键切换功能-FPGA development, implementation around the 8x8 matrix, the on-line scrolling display text. And color display text. By switching function keys
fangbo--quartus
- VHDL语言编写的FPGA产生方波的程序，可供参考-VHDL program language to write the FPGA to produce square wave, for reference
pinlvji
- 数字频率计 实现对1Hz-10KHz频率信号的检测以及超量程警示-The digital frequency meter To detect the 1Hz-10KHz frequency signal and overrange alert
pinlvjitest
- 数字频率计的testbench测试程序，和数字频率计配合使用，该程序实现对输入信号和测试信号的提供。-Digital frequency meter testbench testing procedures, and the digital frequency meter with the use of the program on the input signal and the test signal is provided.
led
- LED译码电路设计，实现LED显示以及扫描电路。该程序采用共阴极。主要的两点为能够自动适应扫描电路的路数.-LED decoder circuit design, implementation, LED display, and the scanning circuit. The program uses a common cathode. The main points to be able to automatically adapt to the large ones scanning c
ledtest
- 数码管译码电路的测试程序，使用modlesim进行测试。该文件和led.rar配合测试使用，如果不需要测试，无需下载该文件。led.rar使用的是模块化设计，分为几个vhdl文件。-Digital decoding circuit test program, using modlesim tested. The documents and led.rar with testing, if you do not test, without having to download the file.
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
addercs16.v
- 这是自己写的 16 bits carry select adder 的verilog的代码，如果有用fell free to download-It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
fulladder.v
- 自己写的full adder的verilog代码，请大家下载。如果有问题请评论给我-Write your own full adder verilog code, please download. If you have questions, please give me a comment