资源列表
DACtoADCtoSPI_Triangle1
- DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
5-example_IR_1
- 基于altera EP4C FPGA的红外解析,协议格式为NEC protocol-FPGA, EP4C, NEC protocol
jishuxianshi
- 用VHDL语言，实现计数显示电路的设计。-Using VHDL language, counter display circuit design.
greytobinary
- grey to binary converter in vhdl
adder
- 四位二进制串行加法器 VHDL语言 EPM240 数字逻辑实验-Four serial binary adder VHDL language EPM240 digital logic test
video_monitor
- 基于FPGA的便携式防盗监控系统的设计与实现-Design and implementation of FPGA-based portable security monitoring system
Nexys3_EDK_GPIO_UART_AXI-14-4
- uart-usb 接口 edk nexys3 德致伦
FPGA-VHDL-Time-Constraints-example
- FPGA VHDL Time Constraints Example
DE2_70_D5M_XVGA
- 针对DE2修改的工程文件，可以正常输出1280*1024的视频图像，并且可以自行进行源码的修改-For DE2 modified project file, it can output 1280* 1024 video image, and modify the source code can be
16_ps2_keyboard
- 基于NIOS II的键盘驱动设计设计，在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现键盘的控制-NIOS II keyboard-driven design-based design, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems keyboard control
altera
- altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看-altera official variety of useful references, are their own collection, problems can easily view
test8
- xilinx工程文件，test8.v是源代码，实现了逐位进位的加法器、减法器，和逻辑运算功能。运行通过，仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the simulation is successful.