资源列表
8B_10BENCODER
- 基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。-8B10B encoder
pwm
- VERILOG 学习第一课，输出一定占空比方波-VERILOG learn the first lesson, a certain duty cycle square wave output
ethernet_test_top
- Ethernet Code for Spartan6 FPGA
ECC in VHDL
- ECC Cryptography in VHDL . Very Helpful for showing
ECC in VHDL implementation
- ECC Cryptography is a very Good Cryptography Compared to other public key cryptography, it is helpful for both computationally intensive and resource constrained devices for information security purpose. hope you will enjoy
CNT999
- 使用VHDL设计999加法计数器，并使用扫描译码电路将数字显示在数码管上。顶层设计使用的原理图-Design using VHDL adder 999 counters, and use the digital scan decode circuit in the digital tube display. Schematic top-level design using
Verilog-tutorial
- verilog语言教程 HDL语言的速成指南-Quick Guide verilog HDL language language tutorial
fir
- FIR滤波器的FPGA仿真与实现。欢迎分享，分享快乐。-The FPGA simulation and realization of the FIR filter.Welcome to share, share the happiness.
matlab
- matlab中的无线信道仿真与实现。欢迎分享，分享快乐。-The wireless channel simulation and realization in matlab.Welcome to share, share the happiness.
reg_16
- 16位寄存器 16位寄存器 -16-bit register,16-bit register16-bit register
fpga
- 线性分组码的FPGA仿真与实现。欢迎分享，分享快乐。-The FPGA simulation and realization of the linear block code.Welcome to share, share the happiness.
CCSDS_H1_yxiao
- CCSDS标准的LDPC编码的MATLAB仿真源码-CCSDS standard LDPC coding MATLAB simulation source