资源列表
Dual_7segment_display
- Verilog code for seven segment disply
4bit_adder
- 4-Bit adder with single bit adder
invaders_multi_rel0001
- XILINX FPGA 游戏实例，包括键盘控制，学习FPGA的好材料-XILINX FPGA game examples, including keyboard control, FPGA good learning materials
DAC8812
- 控制16Bit的D/A芯片DAC8812的FPGA的VHDL代码-FPGA Code control DAC8812
fir18
- 介绍了一种基于FPGA和高精度A/D转换器结合的FIR滤波器电路系统,该滤波器采用乘法累加器算法,并利用X ilinx公司XC3S500E的FPGA进行试验验证,主要包括对输入的正弦波信号进行A/D转换后进行滤波,通过上位机显示滤波结果。 -Introduces an FPGA-based FIR filter circuit systems and high-precision A/D converter combined, the filter algorithm using multipl
cun
- 一个四个地址的四位寄存器，实现存储、读取功能，并在数码管上显示数据的地址-A four addresses four registers for storage, read function, and displays the address of the data on the digital
taxi2
- 出租车计程计费器 vhdl程序 数码管显示路程 车费-Metered taxi meter vhdl program
ADS828-DAC902-VHDL
- ADS828 DAC的VHDL程序 绝对-ADS828 DAC program based on vhdl
VGA
- VGA屏幕显示，verilog语言，分模块文件rtl_test_vga_grid，vga_grid，vga_signal，vga_sync，希望对您有用。-VGA，verilog language，module are rtl_test_vga_grid，vga_grid，vga_signal，vga_sync，i help it s useful to you .
SBcalculator
- fpga简易二进制输入十进制输出计算器，八位拨码开关输入，四位数码管输出。开发板：Spartan 3E XC3S100E CP132 -5-A simple binary-decimal calculator. Spartan 3E XC3S100E CP132 -5
SpaceWire_IP_Rev1p06
- 日本大学开发的SpaceWire IP核，经过多年的改进，已经是第六个版本-Japanese universities developed SpaceWire IP core, after years of improvement, it is already the sixth edition
pwm_ok_PWM
- 用VHDL实现占空比任意可调的PWM产生器。（程序逐行注释），有仿真图。PWM,即Pulse-Width Modulation 脉宽调制，常用于电机的控制中。-Using VHDL adjustable duty cycle of PWM generator. (Progressive program notes), a simulation map. PWM, i.e. Pulse-Width Modulation PWM, used to control the motor.