资源列表
Taximeter
- VHDL出租车计价器，包含所有代码及其仿真结果-VHDL Taximeter that contains all the code and the simulation results
Altera_FIFO
- Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
Modelsim
- Modelsim简明使用手册，十分适合新手使用-Modelsim concise user manual is very suitable for novice to use
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
VHDL-Handbook
- VHDL handbook is very nice and suitable guide to HVDL language
LC_txmit
- FPGA UART transmit and so on
FPGATIMEING
- TIMING LEARNING -TIMING LEARNING
PCi_Bridge
- Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see
DDS
- 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of t
shumaguan
- fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda