资源列表
fifo
- fifo使用手册，对于用IP core使用非常方便-fifo manual, for use with the IP core is very convenient
2-10
- verilog写的2进制转换10机制代码-source for 2~10 with verilog
EDA
- 通过MAXPLUS软件做时钟信号发生器，可通过外部的拨码开关进行清零和预置数-Software made by MAXPLUS clock signal generator is available through an external DIP switch and preset number of cleared
soc_design
- 一款介绍Soc使用的PDF文档供大家看和实践，还是有一定参考价值的！-A descr iption Soc using PDF documents for everyone to see and practice, there are still some reference value!
example7
- 交通灯控制例程；本实验是模拟控制一个十字路口的交通灯，4行3色灯，分别代表一个十字路口的4个口的交通灯。-Traffic light control routines this experiment is the analog control a crossroads, traffic lights, four-line three-color lights, representing an intersection of the four port traffic lights
The_Ten_Commands_of_Excellent_Design
- 介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处-Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary
synmodule
- 设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
verilog
- verilog 入门概述 新手学习资料-Getting Started with an overview of novice learning materials verilog
taxi
- 出租车自动计费系统，功能完善，方便快捷，十分好用-taxi
VerilogHDL
- VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
VHDL_A_Logic_Synthesis_Approach
- vhdl programming from beginner level