资源列表
stopwatchVHDL
- Stopwatch program in VHDL using Xilinx.
fpga_debounce_filter
- fpga debounce filter code in vhdl
rams
- several examples of accessing SRAM in Spartan3
512
- several examples in Sram access in Spatan 3E
vhdl4
- program for full adder.
vhdl2
- 2 programs of basic gates.
vhdlprograms
- uploaded files include vhdl for basic gates.
mul
- baugh wooley multiplier with two four bit input and eight bit output
ModelSimweisijiaocheng
- modelsim 使用流程，一个记数仿真器详细设计步骤， FORCE和RUN两个命令解释，TestBench的一个例子。-modelsim using the process, a detailed design of the emulator counting steps, FORCE, and RUN 2 command interpreter, TestBench an example.
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
XILINX
- Xilinx ebook quick reference guide
Verilog_HDL_9807
- verilog HDL ebook for quick guide