资源列表
xilinx_labs.tar
- quick start EDK xilinx labs
adc_vhdl.tar
- control adc vhdl code spartan 3e starter board
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
sdmrstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
sdmrbeh
- This code implements the behavioral modelling of a Moore type sequence detector to detect the sequence 1010. The code is a quartus project file
sdmlstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
sdmlbeh
- This code implements the behavioral modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file.
DE1_NIOS
- Altera DE1的NIOS源程序，非常有参考价值,可直接投入使用-the niosII project of Altera DE1 borad. It can be used directly
sin_cos
- 运用Lattice IC 产生DDS功能-Lattice IC generated using DDS features
uart
- 用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
vani_tut
- A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist