资源列表
timer
- 数字秒表，按键+数码管 上电后数码管开始计时，精度1/10秒： 按 SW2 ：复位（清零后重新计数） 按 SW3 ：暂停 按 SW4 ：继续计数-Digital stopwatch, key+ digital tube after power digital control start timing, precision 1/10 sec: Press SW2: Reset (after a re-count is cleared) by SW3: Pause Press SW4
music
- 用VHDL 语言设计实现一个10 秒倒计时电路，要求使用8×8 点阵显示计时结果。能在计时到0后开始播放乐曲，同时乐曲可以自由转换。-VHDL Language Design and Implementation with a 10 seconds countdown circuits require the use of 8 × 8 dot matrix display time results. To 0 in time to start playing after the music, a
debounce1
- Debouncing Circuit implementing the Testing Circuit show in the Illustration 1. The input of verification is from a push button switch. In the lower part, the signal is first fed to a debouncing circuit and the to a rising edge detector.
de-
- 任意波形手绘发生器,图片+论文(含有部分源码) 来源ourdev-Arbitrary waveform generator, hand-painted, photo+ paper (containing part of the source) source ourdev
ddr-sdram
- DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
I2C-verilog-(非常详细的i2c学习心得)
- i2c学习心得，详细的I2C VERILOG实现代码(i2c learning experience, detailed I2C VERILOG implementation code)
Zoom-forward-a-relay-relay-network
- 放大转发中继网络中的一种中继选择方案 放大转发中继网络中的一种中继选择方案-Zoom forward a relay relay network relay option to enlarge the network to forward a relay option
BIST-CODE
- BIST IS A BUILT IN SELF TEST FOR VHDL
ADC_3Channal
- Actel FPGA 3通道同时采样程序-Actel FPGA 3 Channel Sample Program
ofdm_modulation_v72
- 基于altera 芯片得ofdm调制解调源程序-Altera chips were based on OFDM modulation and demodulation source
60_binary_counter_vhdl_quartus2
- 一个60进制的计数器的VHDL源代码，测试可行。-a VHDL code of 60 binary counter and it test feasible.
FPGAdesignrule
- 一个很好的讲稿，希望大家多提意见，呵呵。-A very good scr ipt, hope that we do so, huh, huh.