资源列表
dpram
- 在quartus ii平台上，通过代码实现DPRAM，文件夹中包含仿真文件。(generate DPRAM through verilog)
0f1cc5d09c0d
- 自己编写的DDS发生器，方波、三角波、正弦波、还可以输入任意的波形文件-I have written DDS generator, square wave, triangle wave, sine wave, you can enter an arbitrary waveform file
freqm
- Control of a frequency meter example
LCDDriver-ML505-EDK10-1
- Sourcecode on MicroBlade processor for LCD driver on ML505 Xilinx Board
uart_lcd
- 串口控制LCD1602显示的源码 开发软件：Quartus II 9.0 (32-Bit) 硬件：EP1C12-Serial control the the LCD1602 display of source development software: Quartus II 9.0 (32-Bit) Hardware: EP1C12
uboot
- Sample of Uboot for virtex-4 FPGA
ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature
shiyan2
- FPGA换流的实验程序，因为没有信号发生器，无法给出4路PWM信号，就自己产生了开关状态信号，给换流用的-In other experimental procedures FPGA flow, because there is no signal generator, can not give four PWM signal generated on their own switch state signal converter used to
DDS
- 基于FPGA的直接数字频率合成技术的源代码-Direct digital frequency synthesis
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
VHDL
- vhdl 相关知识 指令及示例 和 Physical Level Design using Synopsys-vhdl command and example of relevant knowledge and Physical Level Design using Synopsys
Synchronous-16x8-SRAM-design
- This a book about RAM design-This is a book about RAM design