资源列表
clk1hz
- 分频电路 将电路分频为1赫兹 可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
Introduction-_FPGA
- fpga的初级教程，分为一和二，请认真学习-fpga primary curriculum is divided into one and two, please carefully study
Introduction-_FPGA_mid1
- fpga的中级教程，中级1_逻辑代数基础，请认真学习-fpga intermediate tutorial, intermediate algebra 1_ logical basis, carefully study
Introduction-_FPGA_mid2
- fpga的中级教程，中级2_数字电路基础，请认真学习-fpga intermediate tutorial, intermediate 2_ digital circuits based on carefully study
Introduction-_FPGA_mid3
- fpga的中级教程，中级3_数字电路提高，请认真学习-fpga intermediate tutorial, intermediate 3_ improve digital circuits, carefully study
Introduction-_FPGA_mid4
- fpga的中级教程，中级4_硬件描述语言，请认真学习-fpga intermediate tutorial, intermediate 4_ hardware descr iption language, to seriously study
clock-design-code-for-reference
- 时钟设计参考代码（quartersII）-clock design code for reference
project
- VHDL编写8*8LED点阵。实现显示，滚动字符。包含硬件部分PCB图。-VHDL, 8* 8LED lattice. Achieve the display, scrolling characters. Includes hardware part PCB.
mouse_led
- mouse to led movements to realize where the x and y coordinates. After the first falling-edge tick and the rx-en signal are asserted, the FSMD shifts in the start bit and moves to the dps state. Since the received data is in fixed format, we shift
sssd
- MB CARD FPGA ENTERANCE FOR production lines to inc. process quality and monitoring process step by step phase for better under standing of manufac turing
ac97_latest.tar
- AC97 verilog source code
time
- 年月日时分秒计时器,基于VHDL的表，爱爱爱啊-YYMMDDHHMMSS timer