资源列表
clockVHDL
- 采用自顶向下设计方法，由秒计数模块、分计数模块、时计数模块、时间设置模块和译码模块五部分组成。-Using top-down design methodology, from the second counter module, sub-counting module, when the counting module, time setting module and decoding module of five parts.
7500OK
- 7500液体机,有需要的朋友可以下载，主要就是步时接膜-7500 liquid machine, a friend in need can be downloaded, then when the film is mainly step
UCF_FILES
- FPGA管脚分配资料，spanten3E！-FPGA！！！！！！！！！！！！！！
clock
- 利用VHDL语言实现了时、分、秒的计时，并在七段数码管显示出来。-Using VHDL language realize the hours, minutes and seconds of time, and in the seven-segment LED display.
tlc3
- 一款频率计，可以再XILIX开发板上实现频率计功能，4为数码管显示-One frequency, we can xilix development board to the frequency, 4 for the control display
bb
- CPLD可编程逻辑芯片上实现信号发生器的方法和步骤，系统采用自顶向下的设计方法，以硬件描述语言VHDL和原理图为设计输入，利用模块化单元构建系统。-CPLD programmable logic chip Signal Generator methods and steps system uses top-down design approach to hardware descr iption language VHDL and principles of map design input,
microwave
- 这是用VHDL语言编译的微波炉控制器的源程序，供大家参考。其中包括扫描显示、计数器等部分。-This is compiled with VHDL, microwave oven controller of the source, for your reference. These include scanning display, counters and other parts.
uart_verilog
- 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20
divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
microblaze_lab3
- spartan3e microblaze软核使用范例教程lab3源代码-the use of soft-core spartan3e microblaze tutorial example source code lab3
lab4_4
- 用VHDL实现16进制到10进制以及10进制到16进制的转换-Using VHDL 16 to 229 10 to 16 hex and 10 hex hex conversion
sevenvote
- 本设计师一个7人表决器，用7个开关作为7个输入变量，输入变量是 1 时表示赞同，输入变量为 0 时表示不赞同。-The designer of a voting machine 7 with 7 switch 7 as input variables, input variables is a' 1 ' when agreed input variables for the' 0' that do not agree with.