- HP-UXSystemandNetworkAdministrationII 主要是介绍惠普小型机UNIX系统和网络管理的相关知识
- XUNJIXIAOCHE
- Discrimination-Dictionary-Learning Metaface Learning for Sparse Fisher Discrimination Dictionary Learning for Sparse Representation
- radard this the sar radar signal processing and image display code
- documentgetdoctypenodtd Retrieve the XML document without a DTD and invoke the "getDoctype()" method. It should return null.
- udpjb Relief计算分类权重
资源列表
LED控制VHDL程序与仿真
- FPGA驱动LED静态显示 FPGA驱动LED动态显示（4位）
LEDVHDL
- FPGA驱动LED静态显示 FPGA驱动LED动态显示（4位）-FPGA-driven FPGA-driven LED Display LED static dynamic display (4)
youxi
- 一个游戏程序vhdl源码，供大家参考，希望有兴趣的人下载
Sinusoidal-signal-generator-design
- 正弦信号发生器设计，简单组合电路的设计，多层次电路设计-Sinusoidal signal generator design，Simple combinational circuit design, multi-level circuit design
Xilinx-ISE-14v_license
- Xilinx ISE 14v_license文件，完全可以使用。-The the Xilinx ISE 14v_license file can use.
frequency_meter_VHDL
- 一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
LED
- 一个LED显示动态扫描方式的vhdl实现
frequency_measuement
- 通过基4-fft算法测128点频率模块,其中包含所有需要的vhd文件，但是由于最多100M内容，因而需要用到的ipcore需自己添加。-128 points frequency measurement through based4-fft method,the folder involves all .vhl file,but it don t involves the ipcore due to the100M limit.
OS_CFAR
- the package contains the implementation of order statistic CFAR processor
ulaw.rar
- 使用VHDL语言，实现通信脉冲编码调制（PCM）的u律压缩。,Using VHDL language, the realization of communication pulse code modulation (PCM) of u law compression.
adder
- This the adder VHDL code, it contains input and output fild, also simulate file-adder
rx_fifo
- verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx