资源列表
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
c8051
- 8051单片机设计主程序 顶层文件 顶层文件端口连接-8051 design of the main top-level file
sinc3filter.rar
- 实现sinc3 FILTER的VHDL源码，还有实现SPI通讯的。,Sinc3 FILTER to achieve the VHDL source code, as well as the realization of SPI communication.
Autoseller
- 基于VHDL开发的自动售货机系统，可实现自动售货过程中的基本功能，具有一定的代表性。-VHDL-based development of a vending machine system which can automatically process the basic functions of sales, with a certain representativeness.
Sim_counter
- VHDL 在modelsim上进行前仿真，综合仿真以及时序仿真需要文件（以一个简单计数器为例）-On the front in modelsim VHDL simulation, synthesis and timing simulation requires a simulation file (a simple counter example)
calendar
- 基于fpga的电子日历的设计，用vhdl编写-calendar design based on fpga
huffmancode
- 哈夫曼编码，非最优编码做了功能实现，最优编码程序仍然存在问题-Huffman coding, non-optimal coding done function, the optimal coding process is still a problem
ps2_mouse_interface
- ps2接口的鼠标与vga接口的驱动程序，Verilog HDL语言，运用于FPGA-ps2_mouse_interface and vga in Verilog HDL language, applied to FPGA
fp_top
- 在任意小数分频程序中加入了UART接收模块，可以接收分频系数并实现分频。-In any fractional program joined the UART receiver module can receive the frequency factor and achieve frequency.
CPLD_CODE12
- 最后一个了，其他的未经验证，以后验证成功后再上传-final one, the other is untested and proved to be successful, then later upload
costas
- 载波同步，costas环，基于Verilog的载波同步环-Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
spartan_3e
- sfdg cfd dfg cdfg fdgsdfgzfxgery ityhj tuot kyuo fuykf t7y jty jgfjtyikhgm -sfdg cfd dfg cdfg dfg fdgsdfgzfxgery ityhj tuot kyuo fuykf t7y jty jgfjtyikhgm