资源列表
VHDL源代码2
- VHDL与源代码包-and VHDL source code
huazhong-keda
- 飞思卡尔电动车程序，改程序为华中科技大学的程序，很完整希望大家喜欢！-Freescale electric car program, change the procedure for the Huazhong University of Science program, it is full hope you like!
AdcToplevel
- -- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcToplevel -- Purpose: FPGA interface to a Texas Instruments ADC -- Tools: ISE, XST -- Limitations: none--- Device: Virtex-5 -- Author: Marc Defossez -- Entity Name: AdcTopl
uart_rxd
- NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.
62NIOS_II__driver
- dm9000 nios 下的驱动 fpga网络开发-failed to translate
zyj
- 包含了电子时钟的主要功能,输入CLK为1KHZ,输出为动态扫描8段CLD显示.有闹铃,正点报时,时间调整.调整时能够闪烁显示.本时钟为24小时制.课程设计优秀通过.运行平台:MAX+PLUS2.
rfcs_top
- 带有PPC405的Xilinx FPGA通过CPLD实现远程配置的设计
5-verilog-programs
- the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
MSK_top
- 基于verilog的MSK调制的程序，调试通过，有需要可以下载来参考 -Based on the MSK modulation verilog program, debugging through, there is a need to reference download
Buf_FiFo
- verilog 编写的FIFO，里边有IP核和控制模块，-verilog write FIFO, inside the IP core and control module,
res
- verilog下fpga4路抢答器，有数码管显示和蜂鸣-verilog next fpga4 Road Responder, a digital display and buzzer
RLS.v
- 用verilog实现的一个2抽头RLS自适应滤波器的代码-A realization with verilog HDL code of a two-tap RLS adaprive fliter