资源列表
clock
- 设计一台能显示时、分、秒的数字电子钟，具体要求如下： （1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路； （2）可手动校时，能分别进行时、分的校正； （3）能实现整点报时功能。 -Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the cou
yu
- 25实验二十五：利用程序实现串口RS232与电脑通信-In 25 experiments: Twenty-five by software RS232 serial communication with the computer
VHDL
- 有一个实际的十字路口设置有东西、南北两个方向的干道,为确保车辆安全通行,在每条干道的每个入口设置了一组两位数码管显示装置和四组红、绿、黄信号灯,分别用来指示东西方向直行、南北方向直行、东西方向转弯和南北方向转弯；同时设有紧急处理状态，数码管显示可有人工控制，并设有初始化功能。-There is a real crossroads to set something, the north-south trunk road in both directions, to ensure the safe
FPGA9_VGAaUART
- 基于FPGA Verilog VGA 显示 UART 数据-Based on the FPGA Verilog VGA display UART data
uart_T01
- 用Verilog代码编写，实现串口发送通讯。-Written in Verilog code, the serial port to send communications to achieve.
DE2_VGA1
- Altera DE2 VGA显示实验，VGA显示DLA算法模拟-Altera DE2 VGA display experiment, VGA display DLA algorithm simulation
stopwatch
- 基于Xilinx Spartan3E的秒表，能实现计时两次的功能-Based on the Xilinx Spartan3E stopwatch, time to achieve the functions of the two
bch-code
- this a bch code wich is in visual c-this is a bch code wich is in visual c++
VHDL-qiangdaqi
- VHDL语言实现的抢答器功能，源码和原理图都包含在文件内，可以直接在FPGA上运行。-The VHDL Responder function, source code and schematics are included in the file, you can run directly on the FPGA.
QII_9.1.tar
- quartus 9 "solution" 2
processor
- The purpose of this project is to design a simple Processor Unit
mac控制器
- mac控制器ip核，语言verilog,开发环境xilinx ise,quartus ii等