资源列表
asdasdasdasd
- 基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
Verilog
- 通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
BuildingtheCPUdatapath
- Building the CPU datapath
SOPC_UART
- altera公司的ep1c240c8n，串口调试程序vhdl\nios ii8.0代码等-altera company ep1c240c8n, serial debugger vhdl \ nios ii8.0 code. .
S1_38yima
- 3-8译码器的VHDL语言实现的源程序代码-3-8Decoder
S9_LED_RUN
- 这是一段用VHDL语言编写的LCD的启动程序-S9_LED_RUN
multi8
- 8位乘法器-multi8
adder32
- 原理图输入法制作的32位加法器-adder32
myjiafa
- 用函数语句实现的加法器-adder-function
adder2-bingxing
- 2位加法器并行操作-2adder
adder16
- adder16 16位加法器-adder16