资源列表
SPWMdaima
- spwm算法的verilog实现 对照论文表示成功-spwm algorithm verilog achieve control papers for success
sindeshengcheng
- 正选函数的产生，由ram生成地址 verilog编写-Being elected function generates an address verilog written by ram
uartdeverilog
- uart的编写 采用verilog 绝对可以用-uart prepared using verilog can definitely use
dds_
- 基于VHDL的DDS 串口控制 ROM 文件由MATLAB生成-dds using VHDL serial control
div
- FPGA用VHDL写的10分频程序，保证可用-FPGA using VHDL written 10 divide procedures to ensure that the available
sv-reference-doc
- systemverilog入门 用于IC验证-for test
proda_FixPt
- Fixed point code of vector multiplication
pso2
- i want VHDL coding for doing my project-i want VHDL coding for doing my project..
pso3
- i want VHDL coding for doing my project
Virtex-6-Family-Overview
- Virtex-6 Family Overview
shifter
- 用vhdl语言采用时序电路(移位寄存器)的方式实现（7，4）循环码编码器-Vhdl language used by the timing circuit (shift register) way to achieve (7,4) cyclic code encoder
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s