资源列表
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计（串行式）-VHDL realization of finite impulse response filter design (Serial)
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
FirFilter
- 对称型线性相位FIR滤波器的VHDL源程序，比直接型FIR滤波器速度快一半-VHDLSourceProgramofFirFilter
div8
- 分频系数为8，分频输出信号占空比为50 的分频器-Frequency factor of 8, sub-frequency output signal duty cycle to 50 of the prescaler
adder
- 一个verilog的源码程序，用于加法器实验程序-A source of verilog procedures, experimental procedures for the adder
VCollide201
- 模型冲突检测，是VCollide的压缩文件。能够检测虚拟物体是否发生碰撞，并返回信息-Model of conflict detection is VCollide the compressed file. Can detect whether a collision between virtual objects, and return information
i2c
- i2c数据传输总线接口的verilog源程序-i2c bus interface procedures verilog
NIOSIIStepbystep
- 基于NOIS2 嵌入式系统开发资料，可以一步一步的指导入门，学习FPGA嵌入式系统开发-study nois2 step by step,for improving your abilities
SOPC_Builder
- SOPC架构建立实例，针对altera公司的DE2开发板，其他开发系统也可以用-based FPGA , SOPC construct experiment
LeiFPGALDPC
- this document is for the difference
fpga
- On a distributed algorithm based on FPGA pipelined FIR filter of the article.
dds
- DDS数字频率合成器，使用很方便，整个工程下载，vhdl语言-DDS digital frequency synthesizer, using the very convenient to download the whole project, vhdl language