资源列表
1
- 实现时钟功能，有计数，复位，调整时间，既秒加一功能等，添加了按键的功能。-The realization of the clock function, count, reset, adjust the time, both function-plus-one seconds, add the button functions.
lcddriver
- 基于FPGA的lcd的驱动程序，用VHDL语言编写-FPGA-based driver lcd with VHDL language
OCM12864
- 含有12864LCD 的正确使用方法，以及指令的设置-12864LCD contain the proper use of methods, as well as set up commands
shuzizhong
- 基于fpga数字钟系统，可以显示时钟，以及报时功能-Fpga-based digital clock system can display the clock, as well as the time function
esm
- 详细介绍了三种高效状态机设计，其中还有PDF格式的说明（英文版）。-Detailed information on the status of the three high-performance design, including descr iption of PDF format (in English).
VerilogHDL_IC
- VerilogHDL_IC设计核心技术实例详解，部分习题源码，-Examples of core technology VerilogHDL_IC detailed design, and some exercises source,
FPGA_overview
- code for fpga is written in verilog,cardinality is a thing which is very important
Adder4
- 本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的-The design is to design a full adder 4 content, is one of four full adder in series from the
sevenvote
- 本设计师一个7人表决器，用7个开关作为7个输入变量，输入变量是 1 时表示赞同，输入变量为 0 时表示不赞同。-The designer of a voting machine 7 with 7 switch 7 as input variables, input variables is a' 1 ' when agreed input variables for the' 0' that do not agree with.
verilog-Perl-3.120.tar
- Verilog Parser in Perl
vhdl
- 抢答器里的基本原程序,抢答模块，计时器电路JSQ的VHDL源程序，译码器电路YMQ的VHDL源程序-VHDL
CPLD_CODE
- CPLD的小程序集合，VHDL语言描述，可直接用quartus打开-CPLD collection of small programs, VHDL language descr iption can be directly opened with quartus