资源列表
IJARCET-VOL-1-ISSUE-traffic_light
- Good document which contains traffic light controller
fwdfwfft
- 4位的16点fft，ccmul为复数乘法器，bfproc为蝶形运算器，输出的结果为四位，每一级都要进行round操作。-4 16-point fft, ccmul for complex multiplier, bfproc for the butterfly operation, a result output is four, each stage should be carried out round operation.
AudioSubSystemStereo
- DE2-115 AUDIOSUBSSTEM
FIR_OVER
- 基于FPGA的FIR滤波器的设计，包括每个模块的设计和顶层原理图。-FIR filter design based on FPGA, including the design and top-level schematic of each module.
DE1_SoC_Audio
- 声音录制、播放的Verilog代码，用于Altera Cyclone V SOC. 写时适配的是DE1-SOC开发板。-Audio recording and playing code for Altera Cyclone V SOC FPGA. Code was designed for DE1-SOC development board, but could be reference for other boards.
spram
- vhdl code of single port ram
dpram
- vhdl code dual port map
chirp
- VHDL CODE Of chirp counter
reg16
- vhdl code of 16 bit register which has 8 bit input and 16 bit output at second count-vhdl code of 16 bit register which has 8 bit input and 16 bit output at second count
universal
- vhdl code of universal shift register which o/p is control by mode input
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
vga
- VGA project for DE0-nano