资源列表
pong2
- fpga starter video game pong2 in verilog
clock
- 秒表的verilog语言实现，个人课程设计代码，已验证！实现显示秒，分，时暂停，修正等功能。-Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.
fpga_mcu_communication
- 本压缩文件是51单片机与Altera_Cyclone fpga串口通信程序，经过硬件实际测试验证可用。-This compressed file is 51 and Altera_Cyclone fpga serial communication program, available through the actual test hardware.
lut_core
- LUT core in VHDL program
freq
- 基于FPGA实现的频率计，希望对大家有所作用。-FPGA-based implementation of the frequency meter, and I hope you all have a role.
s
- counter confn dlatch dreg parity srlatch 源代码-counter confn dlatch dreg parity srlatch source
ad9957-verilog
- 正交调制芯片，.v文件，但是没有说明文件，只能作为参考-Quadrature modulation chip,. V file, but no documentation, only as a reference
code
- 把MII接口接收的4比特并行数据转换为8比特的并行数据输出。-convert 4 bit data to 8 bit data
rms_mean_measure
- Measurement of RMS and Mean value
swfsm
- stopwatch的FSM状态机的代码，可供初学者学习参考如何编写状态机-the finite state machine vhdl code for the simple stopwatch file
vhdlcodes
- full adder for the students lab
RS232
- verilog语言编写的串口收发器，可实现发送什么接受什么的功能，简单修改即可实现想要的功能-verilog UART