资源列表
generic_testbench
- VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
LCD-DISPLAY
- 控制LCD显示小程序-LCD TO DISPLAY
bc_6
- 实现6位数据宽度的并串转换，编译和仿真完美实现,编程环境Quartus.
1243687
- 数字频率计VHDL程序 --文件名：plj.vhd。 --功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz。
plj
- 基于VHDL的简易数字频率计，具体功能不清楚请大家验证！ -Simple VHDL-based digital frequency meter, the specific function is not clear please verify!
phase_measure
- 关于用FPGA测量数字信号源相位差的源代码。用的是verilog语言-FPGA on the use of digital signal phase difference measurement of the source code. Using verilog language
v_fifo16
- VHDL ystem will automatically delete the directory of debug and release, so please do not put files on these two directory.
data_switch
- verilog 实现15bit数据与176bit数据间的相互转换，可根据此代码作一定的修改，可以实现其他位宽数据的转换-verilog to achieve mutual conversion between 15bit data with 176bit data can make certain changes based on this code, you can achieve the conversion of other bit-wide data
AlteraFPGA_LM75.zip
- 周立功的FPGA ARM 51的板子上的温度传感器，本样例基于FPGA用Verilog写的。,Ligong weeks of the FPGA ARM 51 temperature sensors on the board, the FPGA-based sample written using Verilog.
AudioVMix
- 通过SDI信号的行同步，列同步和场同步，并通过对行和列的像素点进行计数限制来输出处理后的SDI数据-SDI signal through the line of synchronization, the column sync and field sync, and through pairs of rows and columns of pixels counted restrictions to the SDI output of processed data
top3
- 用VHDL语言编程设计一个可以基于FPGA电路板应用的数字频率-digital frequency meter
clock_check
- 时钟检测,检测时钟的精度，确保时钟没有问题。测试电路，很好用-time test