资源列表
ok003
- vhdl应用汇编所写的关于电梯的详细程序
aFifo
- This an implementation of an Asynchronous FIFO written in Verilog 2001.-This is an implementation of an Asynchronous FIFO written in Verilog 2001.
dctalgo
- vhdl coding for dct algorithm
top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
dwt2d
- discrete wavelet transform - 2d
wu1_selfcheck_beh_0
- 32位的乘法器，能在ISE软件中进行仿真。能看到仿真效果。-32-bit multiplier, the ISE software simulation. Can see the simulation results.
hld1550
- 简单的脉冲时序控制,用于控制脉冲信号发生器的脉冲信号-timing control
FPGA_Divider
- FPGA实现除法器的功能，并行逻辑计算，输出结果为商和余数。适用于FPGA内部无IP核等的低端FPGA器件上。-Function of Divider based on FPGA logic,output result includes the quotient and remainder. This function is applied to the low-end FPGA devices
bcd2ftsegdec
- FPGA bcd 7 segments display example
fifo
- 同步fifo，可以进行读写操作，使用rom ip核进行存储数据，可以作为参考。-Synchronous fifo, read and write operations can be performed using the rom ip core for storing data can be used as a reference.
sellmachine
- 自动售货机，程序很完美,功能：货物信息存储，进程控制，硬币处理，余额计算，显示等功能-sell machine ,in VHDL
std_logic_signed
- 一套签署arithemtic、转换、及比较STD_LOGIC_VECTOR功能的程序。-A set of signed arithemtic, conversion,and comparision functions for STD_LOGIC_VECTOR.