资源列表
Parall_transfer_seior
- 此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.
memory_write_control
- 实现了外界显示器的自定义avalon接口设计
lcd
- 用FPGA来控制2*16LCD的程序，采用VHDL语言来编写，并且我把他转换为verilog语言，有意者请联系；
Common_adder_verilog_design
- 上传文件为：常用加法器verilog设计.rar-Upload files as follows: common adder verilog design. Rar
verilogDiv
- 高精度的二进制触发电路的verilog 源代码 结果低10位二进制数为小数 -binary divider designed with verilog
viterbidec
- 关于fpga的论文，很有使用价值，希望大家能用的上。-Papers on the fpga, great value, I hope everyone can be the last.
I2Cslave
- i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试
dsp_48e
- dsp48e的使用程序 实现乘累加运算-the code of how to use dsp48e
34_BUS
- 基于VHDL的总线设计的实例，对于设计总线规范的同学可以参考下-vhdl bus data
Adder_Verilog
- 对于Verilog初学者非常实用的代码，帮助了解许多常用的加法器-Very useful for beginners Verilog code to help understand the many commonly used adder
fifofinal
- FIFO verilog学习时的基础编程练习。以8位输入，8位输出为例，输入输出采取不同时钟。 附加testbench。-first in first out
scsa
- Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This proposes a novel variable latency speculative adder based on Han-Carlson parallel- prefi