资源列表
I2C_read
- I2C读程序，通过状态机描叙,仿真达到要求-I2C Reading, depicts through the state machine, called Simulation
userbscan
- xilinx FPGA上使用jtag接口作为用户IO的源码。支持任意位宽度。-Xilinx FPGAs use JTAG interface as user IO source. Support for arbitrary bit width.
divider
- 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的
rs-enc-255-239
- rs encoder21-rs encoder2111111111222222222222222222222222222222222
sc2mig
- Bridge Xilinx MIG - JOP SimpCon
lcd1602
- 1620LCD的显示控制-1620lcd
vhdl2009
- 并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through) -- The code can now achieve a single byte of Transceivers
sva
- sva断言，Assertions on overlapping behaviour with SVA-Assertions on overlapping behaviour with SV
TLC549ADC
- FPGA 控制TLC549的ADC V原代码-The FPGA control TLC549 ADC V source code
motorpasso
- Stepper motor pulse generator. This core receives data through system interconnect fabric (bus slave),generates movements pulse and direction signals and provide a fire signal for printer machines. Need to configure prescaler.
seg
- 七段数码管显示，用CASE语句描述各种开通状态-Seven-Segment LED display, with the CASE statement describes the status of various open
TX_ASYNC_for_module_UART
- Tx Async fpr module UART written in Verilog Libero core generator.-Tx Async fpr module UART written in Verilog Libero core generator.