资源列表
Zet-1.3.1
- 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 int
sd_test
- Verilog语言编写的基于SPI总线的micro SD卡读写程序(SD card access based on FPGA)
10-COUNT
- 实验2设计资料10计数 Quartus 开发平台 压缩包内含有全部工程文件及详细资料说明-Experiment 2 design data 10 counts the Quartus development platform Compressed packet contains all engineering documents and detailed information on the
04_led_test
- verilog 入门 流水灯verilog 入门 verilog 入门 verilog 入门(verilog led test xilinx)
lab1
- edk9.1嵌入式开发实验1代码，关于MB何构造一个简单硬件系统-Embedded Development edk9.1 code in Experiment 1, on the MB He constructed a simple hardware system
16_sd_test
- 基于FPGA的sd text测试，很好的学习资料，大家都来学一学-is very good
PipelineCPU
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
verilog_projects-master
- Multiple useful Verilog examples including a VGA controller
基于IP核的ISE设计流程
- 讲述了在ISE中如何通过建立ip核，使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
SRAM_Proj
- SRAM 读写VERILOG HDL源码-SRAM read and write VERILOG HDL source code
Design-and-test-verilog-hdl
- 《设计与验证Verilog HDL》的随书光盘-Design and test Verilog HDL of CD attached with books
ALTERA_CPLD_and_FPGA_device08_09_27-
- 第4章ALTERA的CPLD与FPGA器件08_09_27嵌入式编程系列-Chapter 4 ALTERA CPLD and FPGA devices in embedded programming series 08_09_27