资源列表
full_demo
- vhdl code for fulll_demo
casacade_leds
- Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.
awg
- 基于FPGA的任意波形发生器源代码，并且添加了上位机发送指令和数据（低八位用来发频率控制字，高八位用来发指令）。-FPGA-based arbitrary waveform generator source code, and add the host computer to send commands and data (low eight frequency control word is used to send high eight used to send commands).
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
decoder_3_8
- 采用VHDL语言编写8线-3线优先编码器，在MAX+plus软件下实现。-Using VHDL language-3 line 8 line priority encoder, in MAX+ Plus software to achieve.
vhdl-led
- 基于VHDL设计LED汉字滚动显示器 pdf 资料-base on vhdl design a led chinese-rolled monitor
sdram_led1
- 用于焊接硬件ＳＤＲＡＭ时调试，FPGA驱动SDRAM看能否工作，led可选用户自定义引脚-Used in the welding of the hardware SDRAM, FPGA driver SDRAM to see whether the work, led optional user defined pin
Altera_I2C_example
- IIC VHDL代码。标准的IIC 总线协议（VHDL）-IIC VHDL
my_vix0903
- 基于Xilinx FPGA 的Spartan3 实现的VXI接口-FPGA VXI interface
vhdl
- 基于fpga的vhdl语言，芯片是ep2c8系列，此代码实现的是秒表显示，毫秒到分的数码管显示，数码管是共阳的，分模块设计的，-The vhdl fpga-based language, the chip is ep2c8 series, this code is implemented stopwatch showed milliseconds to-point digital control, digital control is a total of Yang, the sub-modul
time
- 年月日时分秒计时器,基于VHDL的表，爱爱爱啊-YYMMDDHHMMSS timer
DE2_70_CAMERA
- FPGA摄像头驱动，通过VGA，可以在电脑屏幕上实时显示所采集图像-FPGA camera driver, via VGA, you can capture real-time display of the image on the computer screen