资源列表
carsys
- 倒车雷达，可以完成在3米以内的测距并发出不同的警报声-Reversing radar, can be completed in less than 3 meters distance and send different alert sound
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
duc_ddc_system_generator
- 介绍了在xilinx环境中利用system generator设计数字上变频DUC/数字下变频DDC的流程，对于初学者很有帮助-introduced the design of DUC/DDC using system generator under xilinx, it s quite helpful to fresh
14-FPGA-examples
- 14个FPGA例程包，如用FPGA实现跑马灯。多路选择器等-14 FPGA routines packet, such as using FPGA Marquee. Multiple selector
用FPGA实现DDS信号发生及用MODELSIM仿真
- 该工程是用verilog编写，FPGA内部产生ROM及ADD加法器。ROM中存正弦波信号。文件夹中还包含modelsim仿真。
ad974
- AD974及AD766驱动测试代码.原理图方式直接AD后DA转换观察.-AD974 and AD766 driving test code. Schematics AD directly after the DA conversion observed.
CRC32_D8
- 循环冗余校验编码，CRC32，verilog实现，xilinx平台上验证，结果可用。-CRC coding, CRC32, verilog implementation, verification on xilinx platform, the results are available.
VerilogHDL
- verilog hdl 综合实用教程，一本非常实用易学易懂的书-verilog hdl Comprehensive practical tutorial, a very useful book to learn to understand
sin
- 正弦信号发生器程序,用VERILOG写出。
MIPS-ARM-ALU
- 用verilog描述语言实现的MIPS和ARM的ALU程序。-Verilog descr iption language with the MIPS and ARM ALU program.
ddr
- DDR2内存条在FPGA中的应用,包括内部结构，时序操作和注意事项。-about DDR2 APLLICATION IN FPGA，includ inner instraction timequist and attend.
5.4.5_LMS
- 自动滤波FPGA实现，使用的是VHDL语言！-Automatic filter FPGA implementation using VHDL language!