资源列表
VHDL
- 由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and
可编程IC指南
- 可编程IC指南,cadence , ic design(cadence fpga design)
caculator
- fpga实现了计算器功能，代码烧到altera的板子上可直接运行，别的板子需要把.vhd文件复制并重新生成bit文件-Based on FPGA, I implement a caculator.
CPU
- 使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。-Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.
sdram_test
- 这个是经典的sdram的驱动代码，可能你需要留意下具体的芯片型号，我在里面都有介绍，已调可用，并且真的是非常经典-This is a classic sdram driver code, you may need to pay attention to the specific chip model, which I have introduced in the modulated available and really is very classic
spimaster.tar
- SPI Interface Master Control RTL Verilog Code
xapp290
- 从Xilinx网站上下的，学习FPGA部分动态重配置很好的例子。-from across the Xilinx website, learning some FPGA dynamic reconfigurable good example.
DE2_WEB_QII_60
- ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
spimaster_latest.tar
- 经过验证的LCD控制器的代码，含testbench和说明文档-Proven LCD controller code, including testbench and documentation
nspwm
- 功能：产生SPWM波形，频率，占空比任意可调，输出波形稳定.-Function: generate SPWM waveform, frequency, duty cycle adjustable, the output waveform is stable.
multiprocessor
- 简单的乘法器的内核测试，已经验证通过，VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
time-counter
- 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile