资源列表
52_divider
- 一个可实现多倍（次）分频器VHDL源代码设计
fourkindmultiply
- 给出了几种常用乘法器的设计代码 ，读者通过比较可以得出乘法器的设计方法-Given the design of several common multiplier code, the reader can be drawn by comparing the design method of multipliers
tfel
- ABEL-HDL code for custom Planar EL320.240.36 series TFEL display controller.
wb_master_model
- FPGA I2C主机FPGA代码 verilog-FPGA I2C host FPGA code verilog
float_add_module
- verilog编写的32位浮点数加法器。Start_Sig 和Done_Sig 是控制信号，作为启动和反馈完成，A 和B 是32 位宽的操作数输入信号，Result 则是32 位宽的输出结果。-32bits float add module use Verilog HDL.
yyue
- 音乐小程序，初学者使用参考-small procedures, the use of reference beginners
CORDIC_ATAN.rar
- 使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代,Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations
multiplieur8
- 8 bits classique multiplieur
stbc
- STBC的硬件实现源代码，用Verilog语言写的-STBC hardware to achieve source code, written using Verilog language
controller
- PI controller and its source code
light
- 用VHDL语言实现的交通脉冲控制器代码，包括主干道和支路等-Traffic controllers with pulse code VHDL language, including roads and branch etc.
adctl2
- AD7865的verilog控制逻辑,可四通道一起采样，16位输出，高两位表示采集的通道号-control logic for AD7865