资源列表
yangwenli
- 计费器设计中速度控制模块、里程计数模块、计费计数模块vhdl源代码-accounting device design speed control module, the mileage counter module, billing module count vhdl source code
AD9852
- 数字频率合成器芯片AD9852 的配置文件，HDL级的Verilog代码
Desktop
- 这是一个加法器，使用独特的实现方法，能够简洁方便的实现。-This is an adder, using a unique implementation method can be simple and convenient implementation.
Find_The_Prime
- VHDL 代码，用于查找一个数列的素数搜寻器。-Prime Number comparator
ISE_lab5
- 使用VHDL 语言编写7 段数码管显示程序， 掌握数码管的驱动方法。使用USB 电缆或并口下载线下载逻辑电路到FPGA，并 调试电路使其正常工作。-Using the VHDL language 7-segment display program, for digital control of the driving method. Using the USB cable or parallel port download cable to download logic to FPGA,
atlys
- atlys ddr2 test ucf file generated
AX301
- 黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301-Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301
c18_divider.rar
- 精通verilog HDL语言编程源码之4--常用除法器设计,Proficient in language programming verilog HDL source of 4- Common divider design
display
- 数码管显示程序，支持6个数码管，包括译码和电平检测模块。-Digital tube display program, supports six digital control, including decoding and level detection module.
lfsr
- the LFSR is coded in VHDL, using a structural descr iption, which is instantiated as a separate component in the top-level design. Then we can get a random number by a pseudorandom number generator based on a linear feedback shift register (LFS
spi1
- 使用verilog语言编写的实现cpld EPM570与EEPROM的SPI通信-Using verilog language to achieve cpld EPM570 SPI communication with the EEPROM
DataPathComponent.vhd
- Solo componentes para un single Datapath