资源列表
RS232
- xilinx Sparten3E 串行通信及lcd字符显示
main
- vhdl程序 Uncomment the following lines to use the declarations that are provided for instantiating Xilinx primitive components.
cpld-0832
- VHDL语言编写的DAC0832代码，简短而又易懂，可供参考
top
- 交织的vhdl实现，希望对大家有帮助，同他学习！-VHDL-cutting to achieve, I hope all of you help with his learning!
stepmot
- 主要是对矩阵键盘的Verilog HDL 语言的设计实现-Mainly for matrix keyboard Verilog HDL Language Design and Implementation
p2s
- 实现并串转换,需要的可能下下来自己多研究研究，相信还是可以看懂的-parallel to serial
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success
spartan_3_vga
- The control for a Spartan 3 VGA. Is possible to display every color.
CPLD
- 使用CPLD扩展I / O，控制所有输入和输出引脚读写操作，以及对各片选信号的控制。-The CPLD is used to expand the I/O control read and write control of all input and output pins, as well as the chip select signal.
seg7
- 通过Verilog语言，显示七段数码管，在cycloneI上能正确显示-Verilog language, showing seven-segment LED display correctly, cycloneI
costas_DPSK
- 采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz-Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 79
PWM_Gen_150kHz
- 150KHz PWM Generator with single pulse generation which can be enabled or disabled. Can be used for debug purposes where the required number of PWM pulses can be generated