资源列表
dec.vhd
- vhdl code for a 16 bit decoder design
for-0-9
- this the 7 segmant display -this is the 7 segmant display
mod_6counter
- its a mod 6 counter designed using structural modelling
edashuzipinlvji
- EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计-EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design
rbus2dma
- rbus转dma，2个标准之间的bridge-rbus change to dmamodule
75_RAM
- RAM储存器 用VHDL编写,15位输入端口，8位输出端口，以及片选信号，使能信号，写信号-RAM using VHDL, with 15bits input ports, 8bits outputs and select signal, enable signal and writing signal.
digitalclock
- 简单的时钟显示，用fpga实现。用的cyclone ep1c3t144c8 芯片-A simple clock display, with fpga implementation. Chip with the cyclone ep1c3t144c
8LEDverilog
- //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能： 显示 注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人： 黄道斌 编写日期： 2006/07/13 ----------------
Dip_PB_Led
- 用VHDL写的带有防抖动功能的四位计数器
I2C_write
- I2C写程序，程序设计中使用了状态机，并通过输出给指示灯表明状态。-I2C written procedures, program design using state machine, and through to the output indicator showed the state.
TIMER.rar
- 数字钟 六位数码管显示，有清零端，采用分层设计方式编写,6 digital tube digital clock showed that zero-side, using hierarchical design approach to the preparation of
BramCfg
- xilinx FPGA BramCfg source.