资源列表
DSPCompress
- Quartus ii下dspcompress的文件
p2s
- verilog语言实现的并串转换，适用于quartus环境-the verilog language and string conversion for quartus environment
jfq1
- vhdl和verling hdl 的加法器-VHDL and the Adder.
c15_add
- 精通verilog HDL语言编程源码之1--常用加法器设计-Proficient in programming language source verilog HDL of 1- Common adder design
SIGNAL-GENERATION.vhd
- Signal generation for double data rate
PulseWidth_detector_VHDL
- 通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）-communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)
z_motor_driver
- VERILOG 直流无刷驱动模块，可进一步完善并优化。 已通过测试-VERILOG brushless DC drive module can be further improved and optimized. Has been tested
RIT2008051_Quicksort.tar
- QuickSort with single pivot.and QuickSort with Double Pivot.
tx_buff
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
bpsk_sin
- Program to Generate a BPSK signal in VHDL.
vhdl实现alu的源代码
- VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
8B10B
- 以太网PHY层中的组成部分 8B10B编码器-Part of the Ethernet PHY layer in 8B10B encoder