资源列表
c3
- 在FPGA实现的加法器实现的Veilog代码，应用软件为赛林思公司的ISE9.1-adder Veilog
add_2p
- 2级流水线，使用4元件实现的22位全加器的VHDL语言实现，适用于altera的FPGA
5
- VHDL常用模板之与门、或门。。超实用！vhdl编程必备-VHDL templates of commonly used with the door, or door
code
- included verilog and vhdl source files
FPGA
- FPGA 时钟分频器，包括偶数分频和奇数分频两种，本程序占空比为50-FPGA clock divider, including even and odd frequency division two, 50 duty cycle of the program
LED_UART
- 介绍了UART的始初化，中断的使用，以及如何实现UART接收一段信号与处理-Introduced before the beginning of the UART, interrupt the use of, and how to handle UART receive a signal and
NT7532
- NT7532(COG) LCD测试程序笔段型LCD驱动-NT7532(COG)
SPI_IF
- 本人编写的简易SPI协议，将8位数据和8位地址共16bit信息转换为1bit串行数据输出-SPI protocol
exp_cpu_vhd
- cpu模型，除了时序和显示模块，有两个warning-A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows --a right execution of computing. --ZHANG Hongjie 2010.6.11 -- Warning: Inf
shizhong
- 含有时钟及测试模块，有时分秒年月日周的判定和自动计时跑动功能。-Contains a clock and test modules, month, day and sometimes every second week to determine the timing and automatic running function.
man2uart_latest.tar
- fpga uart串口ip核，源代码例程。-fpga uart ip core
uart
- VHDL语言模拟异步串口程序，实测可用，欢迎下载-uart source design by FPGA