资源列表
ADC_16bit
- 16位ADCverilog hdl 代码
nfft
- fft 傅里叶变换 提供了环境配置、源文件编辑、程 序调试-Fourier transform of the signal processing fft very useful
jipin
- fpga检测输入信号的频率数码管显示可以检测到0HZ-20MHZ的输入频率。包括顶层代码，数码管显示代码，时钟分频代码。-fpga detects the input signal frequency digital display can detect 0HZ-20MHZ input frequency. Including top-level code, digital display code, clock divider code.
ssram.tar
- implemention of ssran in VHDL
pinliji
- 全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
wallace
- wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
password
- password vhdl代码 用于basys2板子-password for basys SJTU STUDENTS
ParallelSerialMult
- 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
15_pwm
- pwm 运行与 altera sopc
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
LCD1602_Driver
- 自己课设上写的基于Verilog的LCD1602驱动器，能自定义字符，16x2显示位均已引出，可以用于纯硬件的电子钟等显示-To write their own lessons based on the LCD1602-based Verilog driver can customize the character, 16x2 display spaces have led to, can be used for pure hardware such as an electronic clock
ADC_AD7866_poll
- Module for AD7866 ADC po-Module for AD7866 ADC poll