资源列表
vhdl_demo2
- 设计PCM30基群帧同步电路1．输入码流DATA，速率为2.04Mb/S；每帧256bit，其中前8bit为帧同步码；偶数帧的帧同步码为10011011，奇数帧的帧同步码为110XXXXX（X为任意值）。 2．系统初始状态为失步态，失步信号FLOSS输出低电平，电路在输入码流里逐比特搜寻同步码，当搜寻到第一个偶帧同步码后，电路转为逐帧搜寻，当连续三帧均正确地搜寻到同步码后，系统状态转为同步态，失步信号输出高电平；否则电路重新进入逐比特搜寻状态。 3．系统处于同步态后，当连续四帧检出的同步
FFT
- FPGA嵌入式 fft 用FPGA实现FFT算法-FPGA fft
shift_light
- 流水灯可以左移右移，可改变代码来改变频率-Water light can be shifted to right or left ,we can verify the code to change the frequency
viterbideoderupdated
- Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
top
- 先将并行数据转换为串行位流，再将串行位流转换为并行数据，两个模块共用一条并行总线和时钟。-First parallel data into a serial bit stream, then the serial bit stream into parallel data, two modules share a parallel bus and a clock.
VHDmimasuo
- 用VHDL编写的具有如下功能的电子密码锁：输入为八位二进制的电子密码锁 输入正确，开锁灯亮，输入错误，开锁警示灯亮，同时发出报警声音，按下复位键，报警消失，具有密码修改功能-Prepared using VHDL has the following features of electronic code lock: eight binary input to enter the correct electronic code lock, unlock lights, wrong, unloc
vhdllock
- 用vhdl设计的8位二进制串行密码锁，设计简单实用-Vhdl design with 8-bit binary serial lock design is simple and practical
RS485
- 此程序用UART1外扩MAX485实现RS-485通信，运行前将TX1和P00 短接，RX1和P01短接，当接收到一个数据后，再将接收到的数据送出。-Expand this program in use UART1 MAX485 RS-485 communication, running before the TX1 and P00 short, short RX1 and P01, then the received data when the receiver to a data send.
dian_ji
- 电机驱动源代码，采用VHDL描述，已在开发板上实现，肯定没问题的。-Motor-driven source code, using VHDL descr iption has been achieved in the development board, and certainly no problem.
dma-NIOSii_3c120
- EP3C120芯片上运行的DMA方式程序，经过验证ok。适合NIOSii代码修改或移植。-program for EP3C120 DMA process.
i2cslave_verilog
- 自己实现的一个i2c slave, 已经用在自己的工程里。好用！-I2C slave.
ad9788_spi_ctrl
- spi driver: Analog Device DAC ad9788 SPI Controller