资源列表
led
- 简单程序，led流水灯设计，基于移位操作-Simple procedures, led water lamp design, based on the shift operation
fp
- FPGA基础程序，分频器的设计及实现，利用计数器实现-FPGA based program, crossover design and implementation, realized by the counter
RAM
- FPGA简单程序，RAM可读可写存储器，容易读懂-FPGA simple program, RAM readable and writable memory, easy to read
seg
- FPGA简单程序，可实现一位数码管显示，从0到9 的循环显示-FPGA simple program, enabling a digital display, the display cycles 0-9
lab_5
- Introduction to learn laboratry with altera quartus II 9.1
verilog-sin
- FPGA开发sin波形，用verilog写的正弦波发生器。-FPGA development sin wave with verilog write sine wave generator
AudioDelay_12bit
- Experimental digital ADC and audio delay using VHDL on Spartan3E 500k
eda-2014020904002
- Realization of DeepPy in Realization of DeepPy in -Realization of DeepPy inRealization of DeepPy inRealization of DeepPy in
sva_lab
- SV验证例子 SV验证例子 -system verilog
usb_test
- verilog通过CY7C68013A实现在xc6slx45下的usb2.0通讯-USB2.0 COMMUNICATION BY CY7C6801 UNDER XC6SLX45
vhdl__example_fza.ir
- useful vhdl example contain adder-mux-counter-ram-shifter-rom-flipflop-useful vhdl example contain adder-mux-counter-ram-shifter-rom-flipflop...
A-novel-approach-to-realize-Built-in-self-test(BI
- A novel approach to realize Built-in-self-test(BIST)