资源列表
FSW
- verilog写的有限状态机（FSW）序列检测，检测到0100_01给出高电平，包含测试文件，Modelsim下仿真成功。-Verilog written finite state machine( FSW) sequence detection, detected 0100_01 given high, including the test file, Modelsim simulation success.
25_ov7670_lcd
- verilog ov7670 捕捉和显示-Verilog ov7670 capture display
uart
- 串口通信，verilog实现FPGA的串口通信，包括发送与接收-Serial communication, Verilog achieve FPGA serial communication, including sending and receiving
20_lcd
- FPGA实现LCD显示，verilog编程控制-FPGA achieve LCD display, Verilog programming control
ps2
- verilog实现对键盘的编解码，实现PS2-Verilog keyboard codec to achieve PS2
cpu_hazard
- cpu的开发流程，包括hazard的处理，我课程作业的大作业，还是有参考价值的-cpu development process, including the hazard of handling large jobs my course work, or a reference value
2-button-pong
- This a game which can be play with 2 player pong game -This is a game which can be play with 2 player pong game
xapp1246-multiboot-bpi
- K7芯片 多核BPI BOOT源代码以及PDF说明-K7 chip multi-core BPI BOOT source code and PDF descr iption
QPSK_v
- 1-bit QPSK code for verilog.
20161122_ff
- MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
20161122_gg
- MD5认证部分的第二轮中包含G函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-FPGA contains one operation in the second round of the G function MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
20161203_hh
- MD5认证部分的第三轮中包含H函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-FPGA third round included H functions in one operation MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II