资源列表
spi_write
- 基于veriloghdl语言的spi接口的写操作功能实现，程序经过了modelsim的仿真和上板的调试，功能正常。-the achieviation of spi interface based on the VerilogHdl language
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
Detection0X47
- verilog DVB 扰码设计 0x47-verilog DVB- scrambling design
rgb1
- 红绿灯交通灯的设计，通过规定时间红绿灯的转变实现交通灯的控制-Traffic light traffic light design, implementation, control traffic lights traffic light changes by a predetermined time
FFT
- 使用VHDL语言实现对快速傅立叶变换算法的实现，并通过仿真验证其正确性。-Using VHDL language implementation for the realization of fast Fourier transform algorithm, and its correctness is validated by computer simulation.
RRController
- Source Code for a Rom/And Ram controller and some sample Op-Codes.Written in components and assembled together.enjoy!
UART_TX
- verilog写的串口发送程序，具有单字节发送和多字节发送功能，附带testbench，可自行验证-verilog write serial transmission program, sending a single byte and multi-byte transmit function, with testbench, can verify their own
UART_RX
- 自己用Verilog写的串口接收程序，有testbench，可实现单字节接收和连续接收，testbench可测功能-Own use Verilog write serial reception procedures, testbench, can achieve single-byte receive and continuous reception, testbench measurable function
answer4
- 数字式竞赛抢答器 设计一个可容纳四组参赛者同时抢答的数字抢答器 1.能判断第一抢答者并报警指示抢答成功，其他组抢答均无效 2.设计倒计时时钟，若提前抢答则对相应的抢答组发出警报-Digital Race Responder Design a can hold four groups of participants at the same time answering the digital answering machine 1. To determine the firs
clock
- 数字时钟设计 设计一个数字时钟 要求:(1)用数码管显示时/分/秒 (2)有时间预置功能 (3)能用蜂鸣器报时-Digital Clock Design Design a digital clock Requirements: (1) with the digital display hours/minutes/seconds (2) has the time preset function
AX301
- 10个在黑金AX301开发板上实现的程序源码工程，程序烧进板子就可使用 内附word详细说明了各个工程功能-10 in the black gold AX301 development board to achieve the program source program, the program can be burned into the board Included in the word a detailed descr iption of the various enginee
testadcom
- XILINX FPGA模拟量采样通信测试 XC6SLX9完成AD采样通过光纤通信上传给XILINX XC6SLX25。-XILINX FPGA XC6SLX9 XC6SLX25